TDA7501

SPI bus mode

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7

SPI bus mode

7.1

Interface protocol

The TDA7501 SPI interface protocol comprises :

●

a subaddress and

●

a sequence of n databytes

each consisting of 8 bits (see Figure 14).

The interface accepts both a positiv (Cpol = 1, Cpha = 1) as well as a negativ (Cpol = 0,

Cpha = 0) clocking scheme. However, the data transmitted has to be valid on the rising

edges of the serial clock SCL.

Figure 14.

Timing diagram for the SPI bus mode.

Table 5.

Switching characteristics (SPI mode)

Figure 15.

Timing diagram for switching characteristic

Symbol

Parameter

Min.

Typ.

Max.

Unit

Serial input clock frequency (SCL)

0

4.0

MHz

Serial data setup time

40

ns

Serial data hold time

40

ns

Serial clock high time width

100

ns

Serial clock low time width

100

ns

Select (SEL) to select (SCL) falling setup time

200

ns

Select (SCL) to select (SEL) rising release time

200

ns

Data rise time

2ms

Data fall time

2ms

Chip select high time

200

ns

SEL

SCL

Cpol=1

SCL

Cpol=0

SDA

SA3

SUBADDRESS

DATA

DATA-n

SA2

SA1

SA0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

D00AU1209

SEL

SCL

SDA

SAx,Dy

Tscl

Tsu

Thld

Twh

Twl

Trel

Tsh

D00AU1208