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TDA7502 数据表(PDF) 13 Page - STMicroelectronics |
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TDA7502 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 25 page ![]() TDA7502 SPI interfaces 13/25 4 SPI interfaces Figure 9. SPI clocking scheme. Table 12. SPI interfaces Symbol Description Min Value Unit Master tsclk Clock cycle 12TDSP ns tdtr Sclk edge to MOSI valid 40 ns tmisosetup MISO setup time 16 ns tmisohold MISO hold time 4 ns tsclkh SCK high time 0.5tsclk ns tsclkl SCK high low 0.5tsclk ns Slave tsclk Clock cycle 12TDSP ns tdtr Sclk edge to MOSI valid 40 ns tmosisetup MOSI setup time 16 ns tmosihold MOSI hold time 4 ns tsclkh SCK high time 0.5tsclk ns tsclkl SCK high low 0.5tsclk ns SS (#37) SCK (#36) SCK (#36) SCK (#36) SCK (#36) MISO, MOSI (#38, #39) INTERNAL STROBE FOR INTERNAL CAPTURE D02AU1362 (CPOL=0, CPHA=0) (CPOL=0, CPHA=1) (CPOL=1, CPHA=0) (CPOL=1, CPHA=1) MSB 654321 LSB In master mode it is only supported CPHA = 0. |
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