5/16

M48Z129Y*, M48Z129V

Figure 4. Block Diagram

OPERATION MODES

The M48Z129Y/V also has its own Power-Fail De-

tect circuit. This control circuitry constantly moni-

tors the supply voltage for an out of tolerance

write protects the SRAM, providing data security in

the midst of unpredictable system operation. As

es to the battery, maintaining data until valid power

is restored.

Table 2. Operating Modes

1. See Table 10., page 12 for details.

AI03608

RST

VSS

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

131,072 x 8

SRAM ARRAY

A0-A16

DQ0-DQ7

E

W

G

POWER

VCC

BL

E

INTERNAL

BATTERY

Mode

E

G

W

DQ0-DQ7

Power

Deselect

4.5 to 5.5V

or

3.0to 3.6V

X

X

High Z

Standby

WRITE

X

Active

READ

Active

READ

High Z

Active

Deselect

(1)

X

X

X

High Z

CMOS Standby

Deselect

X

X

X

High Z

Battery Back-up Mode