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M54HC109 数据表(PDF) 1 Page - STMicroelectronics |
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M54HC109 数据表(HTML) 1 Page - STMicroelectronics |
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1 / 10 page ![]() 1/10 March 2004 s HIGH SPEED : fMAX = 67MHz (TYP.) at VCC =6V s LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C s HIGH NOISE IMMUNITY: VNIH =VNIL =28% VCC (MIN.) s SYMMETRICAL OUTPUT IMPEDANCE: |IOH|= IOL =4mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V s PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 109 s SPACE GRADE-1: ESA SCC QUALIFIED s 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST s NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION s DEVICE FULLY COMPLIANT WITH SCC-9306-048 DESCRIPTION The M54HC109 is an high speed CMOS DUAL J-KFLIPFLOPWITH PRESET AND CLEAR fabricated with silicon gate C2MOS technology. In accordance with the logic level on the J and K input this device changes state on positive going transition of the clock pulse. CLEAR and PRESET are independent of the clock and are accomplished by a logic low on the corresponding input. All inputs are equipped with protection circuits against static discharge and transient excess voltage. M54HC109 RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR PIN CONNECTION ORDER CODES PACKAGE FM EM DILC M54HC109D M54HC109D1 FPC M54HC109K M54HC109K1 DILC-16 FPC-16 |
类似零件编号 - M54HC109 |
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类似说明 - M54HC109 |
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