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March 2004

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HIGH SPEED:

s

LOW POWER DISSIPATION:

s

HIGH NOISE IMMUNITY:

s

SYMMETRICAL OUTPUT IMPEDANCE:

s

BALANCED PROPAGATION DELAYS:

s

WIDE OPERATING VOLTAGE RANGE:

s

PIN AND FUNCTION COMPATIBLE WITH

54 SERIES 137

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SPACE GRADE-1: ESA SCC QUALIFIED

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50 krad QUALIFIED, 100 krad AVAILABLE ON

REQUEST

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NO SEL UNDER HIGH LET HEAVY IONS

IRRADIATION

s

DEVICE FULLY COMPLIANT WITH

SCC-9205-013

DESCRIPTION

The M54HC137 is an high speed CMOS 3 TO 8

LINE DECODER/LATCH (INVERTING) fabricated

This device is a 3 to 8 line decoder with latches on

the three address inputs. When GL goes from low

to high, the addresses present at the select inputs

(A, B, and C) is stored in the latches. As long as

GL remains high no address changes will be

recognized. Output enable pins G1 and G2,

control the state of the outputs independently of

the select or latch-enable inputs. All the outputs

are high unless G1 is high and G2 is low. The

54HC137 is ideally suited for the implementation

of

glitch-free

decoders

in

stored-address

application in bus oriented systems.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

M54HC137

RAD-HARD 3 TO 8 LINE DECODER/LATCH (INVERTING)

PIN CONNECTION

ORDER CODES

PACKAGE

FM

EM

DILC

M54HC137D

M54HC137D1

FPC

M54HC137K

M54HC137K1

DILC-16

FPC-16