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STM704 数据表(PDF) 31 Page - STMicroelectronics

部件名 STM704
功能描述  5V Supervisor with Battery Switchover
PDF  37 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM704 数据表(HTML) 31 Page - STMicroelectronics

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STM690A/692A/703/704/802/805/817/818/819
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.75V to 5.5V for “L” versions; VCC = 4.5V to 5.5V for “M” ver-
sions; and VBAT = 2.8V (except where noted).
2. VCC supply current, logic input leakage, Watchdog functionality, Push-button Reset functionality, PFI functionality, state of RST and
RST tested at VBAT = 3.6V, and VCC = 5.5V. The state of RST or RST and PFO is tested at VCC = VCC (min). Either VCC or VBAT
can go to 0V if the other is greater than 2.0V.
3. VCC (min) = 1.0V for TA = 0°C to +85°C.
4. Tested at VBAT = 3.6V, VCC = 3.5V and 0V.
5. Guaranteed by design.
6. WDI input is designed to be driven by a three-state output device. To float WDI, the “high impedance mode” of the output device
must have a maximum leakage current of 10µA and a maximum output capacitance of 200pF. The output device must also be able
to source and sink at least 200µA when active.
7. When VBAT > VCC > VRST, VOUT remains connected to VCC until VCC drops below VRST.
8. When VRST > VCC > VBAT, VOUT remains connected to VCC until VCC drops below the battery voltage (VBAT) – 75mV.
9. For VCC falling.
Push-button Reset Input (STM703/704/819)
tMLMH
tMR
MR Pulse Width
STM703/704
150
ns
STM819
1
µs
tMLRL
tMRD
MR to RST Output Delay
STM703/704
250
ns
STM819
120
ns
MR Glitch Immunity
STM819
100
ns
MR Pull-up Resistor
MR = 0V, VCC = 5V
45
63
85
k
Ω
Watchdog Timer (NOT available on STM703/704/819)
tWD
Watchdog Timeout Period
VRST (max) < VCC < 5.5V
1.12
1.60
2.24
s
WDI Pulse Width
VRST (max) < VCC < 5.5V
50
ns
Chip-Enable Gating (STM818 only)
E-to-ECON Resistance
VCC = VRST (max)
40
150
Ω
E-to-ECON Propagation Delay
4.5V < VCC < 5.5V
27
ns
Reset-to-ECON High Delay
(Power-down)
15
µs
ECON Short Circuit Current
VCC = 5V, Disable Mode,
E = Logic high, ECON = 0V
0.10.752.0
mA
Sym
Alter-
native
Description
Test Condition(1)
Min
Typ
Max
Unit



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