Detailed description

STCF03I

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9

Detailed description

9.1

PowerON reset

This mode is initiated by applying a supply voltage above the VPW_ON RESET threshold

value. An internal timing (~1 µs) defines the duration of this status. The logic blocks are

powered, but the device doesn't respond to any input. The registers are reset to their default

reading the ADD pin configuration. After the internally defined time has elapsed, the

STCF03I automatically enters the Stand-by mode.

9.2

Shutdown

The device enters this mode: automatically from Power ON Reset status; by resetting the

PWR_ON bit from other operation modes. Power consumption is at the minimum (1 µA typ).

9.3

Ready mode

In this mode all internal blocks are turned ON, but the DC/DC converter is disabled and the

White LED is disconnected. The NTC circuit can be activated to monitor the temperature of

Only in this mode the Auxiliary LED is operational and can be turned ON and set at the

desired brightness using the AUX REGISTER. The device enters this mode: from Stand-by

by setting the PWR_ON bit; from Flash operation by resetting the TRIG pin or the TRIG_EN

bit or automatically from Flash operation when the Time Counter reaches zero; from Torch

operation by resetting the TCH_ON bit. The device automatically enters this mode also

when an overload or an abnormal condition has been detected during Flash or Torch

operation (Table 16: Status register details:).

9.4

Single or multiple Flash using external (µP) temporization

the Flash duration (hard-triggering). The TRIG_EN bit of CMD_REG should be set before

starting each flash operation, because it could have been reset automatically in the previous

Flash operation. The Flash duration is determined by the pulse length that drives the TRIG

pin. As soon as the Flash is activated, the system needs typically 1.2 ms to ramp up the

output current on the Power LED. The internal Time Counter will Time-out Flash operation

and keep the LED dissipated energy within safe limits in case of Software deadlock; FTIM

register has to be set first, either in Stand-by or in Ready Mode. Multiple flashes are possible

by strobing the TRIG pin. Time out counter will cumulate every flash on-time until the

defined time out is reached unless it is reloaded by updating the CMD_REG. After a single

or multiple Flash operations are timed-out, the device automatically goes into Ready mode

by resetting the TRIG_EN bit, and also resets the F_RUN bit. The ATN pin is pulled down to

inform the µP that the STAT_REG has been updated.