1/10

June 2004

s

HIGH SPEED:

s

LOW POWER DISSIPATION:

s

COMPATIBLE WITH TTL OUTPUTS:

s

SYMMETRICAL OUTPUT IMPEDANCE:

s

BALANCED PROPAGATION DELAYS:

s

PIN AND FUNCTION COMPATIBLE WITH

54 SERIES 138

s

DEVICE FULLY COMPLIANT WITH

SCC-9205-022

DESCRIPTION

The M54HCT138 is an high speed CMOS 3 TO 8

LINE DECODER fabricated with silicon gate

If the device is enabled, 3 binary select inputs (A,

B, and C) determine which one of the outputs will

go low. If enable input G1 is held low or either G2A

or G2B is held high, the decoding function is

inhibited and all the 8 outputs go high. Three

enable inputs are provided to ease cascade

connection and application of address decoders

for memory systems.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

M54HCT138

RAD HARD 3 TO 8 LINE DECODER (INVERTING)

PIN CONNECTION

ORDER CODES

PACKAGE

FM

EM

DILC

M54HC138D

M54HC138D1

FPC

M54HC138K

M54HC138K1

Rev. 1

DILC-16

FPC-16