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PM8800ATR 数据表(PDF) 7 Page - STMicroelectronics

部件名 PM8800ATR
功能描述  Integrated IEEE 802.3af compliant PoE-PD interface and PWM controller with support of external source
PDF  35 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

PM8800ATR 数据表(HTML) 7 Page - STMicroelectronics

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PM8800A
Pins description and connection diagrams
7/35
7DCCL
DC current limit.
A resistor between DCCL and VSS will set the current limit for the interface
section of the PM8800A. It can be set to exceed the IEEE802.3af current limit.
Leave the pin open for standard IEEE 802.3af applications.
8
VSS
System low potential input.
9GND
System return for the PWM converter.
It is the drain of the internal hot-swap power MOSFET.
10
GD
Output of the PWM controller. External power MOSFET gate driver output.
11
VCC
Output of the internal high voltage regulator.
When the auxiliary transformer winding (if used) raises the voltage on this pin
above the regulation set point, the internal regulator will be switched off, reducing
the controller power dissipation.
12
nPGD
Power good, active low signal.
A high to low transition indicates that the inrush current phase has been
completed, the internal hot swap MOSFET is fully closed and the SMPS portion of
the PM8800A is activated.
13
CS
Current sense input.
Current sense input for current mode control and over-current protection. Current
limiting is obtained with a dedicated current sense comparator. If the CS pin
voltage exceeds 0.5 V the GD pin switches low for cycle-by-cycle current limiting.
Leading edge blanking is implemented to mask current spikes.
14
COMP
The output of the error amplifier and input of the Pulse Width Modulator.
COMP pull-up is provided by an internal 2.5 k
Ω resistor which may be used to
bias an opto-coupler transistor.
15
VFB
Feedback signal.
Inverting input of the internal error amplifier. The non-inverting input is internally
connected to a 1.25 V reference.
If not used must be grounded to AGND.
16
AGND
Analog PWM supply return.
GND for sensitive analog circuitry including the SMPS current limit circuitry. Must
be connected to GND to improve noise immunity.
EP
Exposed pad.
Connect this to a board plane to improve heat dissipation; must be electrically
connected to VSS
Table 2.
Pin description (continued)
Pin#
Name
Function



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