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ST7LITE1XB 数据表(PDF) 124 Page - STMicroelectronics |
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ST7LITE1XB 数据表(HTML) 124 Page - STMicroelectronics |
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124 / 159 page  ST7LITE1xB 124/159 13.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA. 13.5.1 General Timings Notes: 1. Guaranteed by Design. Not tested in production. 2. Data based on typical application software. 3. Time measured between interrupt event and interrupt vector fetch. Δt c(INST) is the number of tCPU cycles needed to fin- ish the current instruction execution. 4. Data based on design simulation and/or technology characteristics, not tested in production. 13.5.2 External Clock Source Figure 78. Typical Application with an External Clock Source 13.5.3 Auto Wakeup from Halt Oscillator (AWU) Note: 1. Guaranteed by Design. Not tested in production. Symbol Parameter 1) Conditions Min Typ 2) Max Unit tc(INST) Instruction cycle time fCPU=8MHz 23 12 tCPU 250 375 1500 ns tv(IT) Interrupt reaction time 3) tv(IT) = Δtc(INST) + 10 fCPU=8MHz 10 22 tCPU 1.25 2.75 μs Symbol Parameter Conditions Min Typ Max Unit VOSC1H or VCLKIN_H OSC1/CLKIN input pin high level voltage see Figure 78 0.7xVDD VDD V VOSC1L or VCLKIN_L OSC1/CLKIN input pin low level voltage VSS 0.3xVDD tw(OSC1H) or tw(CLKINH) tw(OSC1L) or tw(CLKINL) OSC1/CLKIN high or low time 4) 15 ns tr(OSC1) or tr(CLKIN) tf(OSC1) or tf(CLKIN) OSC1/CLKIN rise or fall time 4) 15 IL OSCx/CLKIN Input leakage current VSS≤VIN≤VDD ±1 μA OSC1/CLKIN OSC2 fOSC EXTERNAL ST72XXX CLOCK SOURCE Not connected internally VOSC1L or VCLKINL VOSC1H or VCLKINH tr(OSC1 or CLKIN)) tf(OSC1 or CLKIN) tw(OSC1H or CLKINH)) tw(OSC1L or CLKINL) IL 90% 10% Symbol Parameter 1) Conditions Min Typ Max Unit fAWU AWU Oscillator Frequency 50 125 250 kHz tRCSRT AWU Oscillator startup time 50 µs |
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