LFXP datasheet(29/130 Pages) LATTICE

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Architecture

Lattice Semiconductor

LatticeXP Family Data Sheet

Table 2-9. Characteristics of Normal, Off and Sleep Modes

SLEEPN Pin Characteristics

The SLEEPN pin behaves as an LVCMOS input with the voltage standard appropriate to the VCC supply for the

device. This pin also has a weak pull-up typically in the order of 10µA along with a Schmidt trigger and glitch ﬁlter to

prevent false triggering. An external pull-up to VCC is recommended when Sleep Mode is not used to ensure the

device stays in normal operation mode. Typically the device enters Sleep Mode several hundred ns after SLEEPN

is held at a valid low and restarts normal operation as speciﬁed in the Sleep Mode Timing table. The AC and DC

speciﬁcations portion of this data sheet show a detailed timing diagram.

Conﬁguration and Testing

The following section describes the conﬁguration and testing features of the LatticeXP family of devices.

IEEE 1149.1-Compliant Boundary Scan Testability

All LatticeXP devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access

port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan

path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in

and loaded directly onto test nodes, or test data to be captured and shifted out for veriﬁcation. The test access port

consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage VCCJ and can

operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards.

For more details on boundary scan test, please see information regarding additional technical documentation at

the end of this data sheet.

Device Conﬁguration

All LatticeXP devices contain two possible ports that can be used for device conﬁguration and programming. The

test access port (TAP), which supports serial conﬁguration, and the sysCONFIG port that supports both byte-wide

and serial conﬁguration.

The non-volatile memory in the LatticeXP can be conﬁgured in three different modes:

• In sysCONFIG mode via the sysCONFIG port. Note this can also be done in background mode.

• In 1532 mode via the 1149.1 port.

• In background mode via the 1149.1 port. This allows the device to be operated while reprogramming takes

place.

The SRAM conﬁguration memory can be conﬁgured in three different ways:

• At power-up via the on-chip non-volatile memory.

• In 1532 mode via the 1149.1 port SRAM direct conﬁguration.

• In sysCONFIG mode via the sysCONFIG port SRAM direct conﬁguration.

Characteristic

Normal

Off

Sleep

SLEEPN Pin

High

—

Low

Static Icc

Typical <100mA

Typical <100uA

I/O Leakage

<10µA

<1mA

<10µA

Power Supplies VCC/VCCIO/VCCAUX

Normal Range

Off

Normal Range

Logic Operation

User Deﬁned

Non Operational

Non operational

I/O Operation

User Deﬁned

Tri-state

JTAG and Programming circuitry

Operational

Non-operational

EBR Contents and Registers

Maintained

Non-maintained

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