STA011 datasheet(19/38 Pages) STMICROELECTRONICS

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STA011

I2C-bus interface

19/38

The master sends the data and each byte isacknowledged by the I2C. The master

terminates the transfer by generating a STOP (P) condition.

The sub-address decides the starting byte. A Multi-byte with sub-address 00H and 5

DATA_IN bytes would affect the bytes starting from DATA_OUT [119:112] to DATA_OUT

[87:80] and so on. A Multi byte with sub-address from the ranges 00H - 0FH produces illegal

sub-address signal to go high, and DATA_OUT[119:0] will not change until a successive

write operation request, with the correct range for sub-address will be made.

5.1.11

Read operation

Current byte address read

For the I2C of STA011 this is the only read mode operation implemented. In the current byte

address read mode, following a START condition, the master sends the device address with

the RW bit set to 1. The I2C acknowledges this and outputs the byte data by reading from

the internal byte address counter. The master does not acknowledge the received byte, but

terminates the transfer with a STOP condition.

This method operation is not used.

Data validity

Figure 5.

Validity on I2C-bus

Timing diagram of the I2C-bus:

Figure 6.

Timing diagram of the I2C-bus

110000A

R/W 0

ack

Sub-address byte

ack

DATA IN

ack

...………

DATA IN

ack

110000A

R/W 1

ack

DATA

No ack

SDA

SCL

DATA LINE

STABLE, DATA

VALID

CHANGE

DATA

ALLOWED

D99AU1031

SCL

SDA

START

I2CBUS

STOP

D99AU1032

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