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STA308A 数据表(PDF) 21 Page - STMicroelectronics

部件名 STA308A
功能描述  Multi-channel digital audio processor with DDX TM
PDF  63 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA308A 数据表(HTML) 21 Page - STMicroelectronics

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STA308A
Registers
21/63
7.2
Register description
7.2.1
Configuration register A (0x00)
The DDX8000 supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4
kHz, 192 kHz, and 2.8224 MHz DSD. Therefore the internal clocks are:
"
65.536 MHz for 32 kHz
"
90.3168 MHz for 44.1 kHz, 88.2 kHz, 176.4 kHz, and DSD
"
98.304 MHz for 48 kHz, 96 kHz, and 192 kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sample
frequency (fs). The relationship between the input clock and the input sample rate is
determined by both the MCSn and the IRn (input rate) register bits. The MCSn bits
determine the PLL factor generating the internal clock and the IRn bits determine the
oversampling ratio used internally.
Interpolation ratio select
The STA308A has variable interpolation (oversampling) settings such that internal
processing and DDX output rates remain consistent. The first processing block interpolates
by either 4 times, 2 times, or 1 time (pass-through).
The oversampling ratio of this interpolation is determined by the IR bits.
D7
D6
D5
D4
D3
D2
D1
D0
COS1
COS0
DSPB
IR1
IR0
MCS2
MCS1
MCS0
10
00
00
11
Bit
RW
RST
Name
Description
0RW
1
MCS0
Master clock select: selects the ratio between the
input I2S sample frequency and the input clock.
1RW
1
MCS1
2RW
0
MCS2
Input sample rate
fs (kHz)
IR
MCS[2:0]
1XX
011
010
001
000
32, 44.1, 48
00
128 * fs
256 * fs
384 * fs
512 * fs
768 * fs
88.2, 96
01
64 * fs
128 * fs
192 * fs
256 * fs
384 * fs
176.4, 192
10
64 * fs
128 * fs
192 * fs
256 * fs
384 * fs
DSD
11
2 * fs
4 * fs
6 * fs
8 * fs
10 * fs
Bit
RW
RST
Name
Description
3
RW
0
IR0
Interpolation ratio select: selects internal
interpolation ratio based on input I2S sample
frequency
4RW
0
IR1



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