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STA323W 数据表(PDF) 40 Page - STMicroelectronics

部件名 STA323W
功能描述  2.1-channel high-efficiency digital audio system
PDF  77 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA323W 数据表(HTML) 40 Page - STMicroelectronics

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Register descriptions
STA323W
40/77
7.2
Configuration register B (address 0x01)
7.2.1
Serial audio input interface format
7.2.2
Serial data interface
The STA323W serial audio input interfaces with standard digital audio components and
accepts several different serial data formats. The STA323W always acts as a slave when
receiving audio input from standard digital audio components. Serial data for two channels
is provided using 3 input pins: left/right clock LRCKI, serial clock BICKI, and serial data SDI.
The SAI register (configuration register B (address 0x01) bits D3-D0) and the SAIFB
register (configuration register B (address 0x01) bit D4) are used to specify the serial data
format. The default serial data format is I2S, MSB first. The formats available are shown in
Figure 46 and in Table 21 and Table 22.
Figure 46.
General serial input and output formats
Table 22. lists the serial audio input formats supported by STA323W when
BICKI = 32 * fs, 48 * fs or 64 * fs, where the sampling rate fs = 32, 44.1, 48, 88.2, 96, 176.4
or 192 kHz.
D7
D6
D5
D4
D3
D2
D1
D0
C2IM
C1IM
DSCKE
SAIFB
SAI3
SAI2
SAI1
SAI0
1
00000
00
Table 21.
Serial audio input interface format
Bit
R/W
RST
Name
Description
3:0
RW
0000
SAI[3:0]
Determines the interface format of the input serial digital
audio interface.
4
RW
0
SAIFB
Data format:
0: MSB first
1: LSB first
I
2S
Left Justified
LRCLK
Left
Right
SCLK
SDATA
LSB
MSB
LSB
MSB
MSB
LRCLK
Left
Right
SCLK
SDATA
LSB
MSB
LSB
MSB
MSB
Right Justified
LRCLK
Left
Right
SCLK
SDATA
LSB
MSB
LSB
MSB
MSB



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