7/11

STA500

Figure 4. Typical Quad Half Bridge Configuration

Note:

The diagran showed below, have been obtained using the demonstration board described in the application

Note AN1456 (STA304 + STA500 Digital Audioprocessor evolution board evaluating manual - Jan 2002), refer

to the schematic shown in fig. 1).

For the Quad Half Bridge Configuration (fig. 4), refers to the application note AN1661 (STA308 Half Bridge

Board - March 2003)

L11 22

µH

L12 22

µH

C51

1

µF

C71

100nF

C91

1

µF

C81

100nF

C31 820

µF

C21

2200

µF

C58

100nF

C58

100nF

R57

10K

R59

10K

R41

20

R61

5K

R62

5K

R51

6

C53

100nF

C60

100nF

C61

100nF

15

M3

IN1A

IN1A

IBIAS

CONFIG

PWRDN

PWRDN

FAULT

TRI-STATE

TH_WAR

TH_WAR

+3.3V

IN1B

GND-Reg

GND-Clean

IN2A

IN1B

IN2A

IN2B

PROTECTIONS

&

LOGIC

REGULATORS

29

23

24

25

27

26

28

30

21

22

33

34

35

36

M2

M5

M4

17

16

OUTPL

PGND1P

OUTPL

14

12

10

11

OUTNL

PGND1N

OUTNL

13

C52

1

µF

C62

100nF

7

M17

M15

M16

M14

8

9

OUTPR

PGND2P

OUTPR

6

4

2

3

OUTNR

PGND2N

D03AU1474

OUTNR

5

19

31

20

GNDSUB

1

IN2B

32

C72

100nF

C92

1

µF

C82

100nF

R52

6

C41

330pF

R42

20

C42

330pF

C32 820

µF

L13 22

µH

L14 22

µH

C73

100nF

C93

1

µF

C83

100nF

C33 820

µF

R43

20

R53

6

C74

100nF

C94

1

µF

C84

100nF

R54

6

C43

330pF

R44

20

C44

330pF

C34 820

µF

R63

5K

R64

5K

R65

5K

R66

5K

R67

5K

R68

5K