ADP2503/ADP2504

Preliminary Technical Data

THEORY OF OPERATION

1.0µH

22µF

BAND GAP

REFERENCE

SYNC

PGND

AGND

EN

PVIN

VBAT = 2.3V

TO 5.5V

VIN

VOUT

SW1

SW2

EN

2.25V

UVLO

10µF

ADP2503/ADP2504

BIASING

ADP2503/ADP2504

PMOS1

PMOS2

NMOS1

NMOS2

THERMAL

PROTECTION

PWM CONTROL

OSCILLATOR

8

4

5

6

7

3

9

FB

–0.5V

2

1

10

CS

SOFT START

Figure 27. ADP2503/ADP2504 Block Diagram

The ADP2503/ADP2504 are synchronous average current-

mode switching buck-boost regulators designed to maintain a

NMOS2 is always off and the switches PMOS1, NMOS1 consti­

the device is in boost mode: PMOS1 is always active, NMOS1 is

always off and the switches NMOS2, PMOS2 constitute a boost

the ADP2503/ADP2504 automatically enter the buck-boost

mode. In buck-boost mode, the two operations buck (PMOS1

and NMOS1 switching in antiphase) and boost (NMOS2 and

PMOS2 switching in antiphase) take place at each period of the

clock. This is aimed at maintaining the regulation and keeping a

minimal current ripple in the inductor to guarantee good

transient performances.

REVERSE CURRENT LIMIT

expected, the inductor current becomes negative (reverse

current). The negative peak value is limited to 1.1 A by

deactivating the switch PMOS2.

POWER SAVE MODE

When the SYNC pin is low, the ADP2503/ADP2504 can operate

in power save mode (PSM). In this mode, when the load

again for a new cycle. This minimizes the switching losses at

light load. When the load rises above 150 mA, the

ADP2503/ADP2504 revert back to fixed PWM mode. This

results in about 75 mA of hysteresis between PSM and fixed

PWM, preventing oscillations between these two modes.

SOFT START

0 V to its final programmed value in 200 μs (typ). This limits

the inrush current to less than 600 mA for a nominal output

the inrush current becomes larger if the output capacitor is

made larger.

Rev. PrB | Page 10 of 16