Preliminary Technical Data

ADP2503/ADP2504

PIN CONFIGURATION AND FUNCTION DESCRIPTION

VOUT 1

*CONNECT PADDLE TO GND.

TOP VIEW

(Not to scale)

ADP2503/

ADP2504

10 FB

SW2 2

9AGND

PGND 3

8VIN

SW1 4

7SYNC

PVIN 5

6EN

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VOUT

The output of the ADP2503/ADP2504. Connect the output capacitor between VOUT and PGND.

2

SW2

Power Switch 2 Connection. This is the internal connection to the input PMOS and NMOS switches.

Connect SW2 to the inductor with a short, wide track.

3

PGND

Power GND. Connect the input and output capacitors and PGND pin to a PGND plane.

4

SW1

Power Switch 1 Connection. This is the internal connection to the output PMOS and NMOS switches.

Connect SW1 to the inductor with a short, wide track.

5

PVIN

Power Input. This the input to the buck-boost power switches. Place a 10 μF capacitor between PVIN and

PGND as close as possible to the ADP2503/ADP2504.

6

EN

Enable. Drive EN high to turn on the ADP2503/ADP2504. Bring EN low to put the part into shutdown

mode.

7

SYNC

The SYNC pin permits the ADP2503/ADP2504 to operate in three different modes.

Normal operation: with SYNC driven low, the ADP2503/ADP2504 operates at 2.5 MHz PWM mode for

heavy and medium loads, and moves to power save mode (PSM) mode for light loads.

Forced PWM operation: with SYNC driven high, the ADP2503/ADP2504 operates at fixed 2.5 MHz PWM

mode for all load conditions.

SYNC mode: to synchronize the ADP2503/ADP2504 switching to an external signal, drive this pin with a

clock between 2.2 MHz and 2.8 MHz. The SYNC signal must have on and off times greater than 160 ns.

8

VIN

Analog Power Supply. This is the supply for the ADP2503/ADP2504 internal circuitry.

9

AGND

Analog Ground.

10

FB

Output Feedback. This is an input to the internal error amplifier.

EP

Paddle

Connect the paddle to PGND.

Rev. PrB | Page 5 of 16