SABRE-LL-I datasheet(21/141 Pages) STMICROELECTRONICS

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SABRE-LL-I

Supervisory system

21/141

Additionally the system regulators will be powered off but only if the voltage that caused the

nRST_int event is checked before the system regulator in the power up sequence. This

means that:

–

all system regulators will be powered off if nRST_int is caused by VSupply,

VSupply_int, VPump (and also if V3v3 causes a POR);

–

no one of the system regulators will be powered off if nRST_int is caused by

VGPIO_SPI;

–

only the system regulators that follows the system regulator that caused the

nRST_int in power up sequence will be powered off.

5.4

nRESET specifications

Table 9.

nRESET circuit specifications

Parameter

Description

Test

condition

Min

Typ

Max

Unit

nRST_VOL

nRESET Low level output

voltage

I=10mA

0.4

nRST_fall

nRESET fall time

I=1mA

C=50pF(1)

Measured between 10% and 90% of output voltage transition.

nRST_del

nRESET delay time

(2)

Measured from a fault detection to 50% of output voltage transition.

150

VSupply_UV_f

VSupply falling threshold

18.5

VSupply_UV_r

VSupply rising threshold

VSupply_UV_hys

VSupply hysteresis

tSupply_UV

VSupply UV filter time

3.5

VS_Int_UV_f

VSupplyInt falling threshold

14.0

VS_Int_UV_r

VSupplyInt rising threshold

17.5

VS_Int_UV_hys

VSupplyInt hysteresis

1.5

tS_Int_UV

VSupplyInt UV filter time

3.5

µs

VPump_UV_f

VPump falling threshold

VSupply

VPump_UV_r

VPump rising threshold

VSupply

+ 9.5

VPump_UV_hys

VPump hysteresis

1.5

tPump_UV

VPump UV filter time

3.5

VGPIO_SPI_UV_f VGPIO_SPI falling threshold

1.8

VGPIO_SPI_UVr

VGPIO_SPI rising threshold

2.4

VGPIO_SPI_hys

VGPIO_SPI hysteresis

250

tGPIO_SPI_UV

VGPIO_SPI UV filter time

3.5

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