STE2002_06 datasheet(21/61 Pages) STMICROELECTRONICS

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STE2002

Instruction set

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Instruction set

Two different instructions formats are provided:

- With D/C set to LOW

commands are sent to the Control circuitry.

- With D/C set to HIGH

the Data RAM is addressed.

Two different instruction set are embedded: the STE2001-like instruction set and the

extended instruction set. To select the STE2001-like instruction set the EXT pad has to be

connected to a logic LOW (connect to VSS). To select the extended instruction the EXT pad

has to be connected to a logic HIGH (connect to VDD1).

The instructions have the syntax summarized in

Table 10, (basic-set) and Table 11

(extended set).

4.1

Reset (RES)

At power-on, all internal registers are configured with the default value. The RAM content is

not defined. A Reset pulse on RES pad (active low) re-initialize the internal registers content

(see

Table 10, Table 11, Table 12). Applying a reset pulse, every on-going communication

with the host controller is interrupted. After the power-on, the Software Reset instruction can

be used to re-load the reset configuration into the internal registers

The default configurations is: .

A MEMORY BLANK instruction can be executed to clear the RAM content.

4.2

Power down (PD = 1)

When at Power Down, all LCD outputs are kept at VSS (display off). Bias generator and

VLCD generator are OFF (VLCDOUT output is discharged to VSS, and then is possible to

disconnect VLCDOUT). The internal Oscillator is in off state. An external clock can be

provided. The RAM contents is not cleared.

- Horizontal addressing (V = 0)

- Normal instruction set (H[1:0] = 0)

- Normal display (MX = MY = 0)

- Display blank (E = D = 0)

- Address counter X[6: 0] = 0 and Y[4: 0] = 0

- Temperature coefficient (TC[1: 0] = 0)

- Bias system (BS[2: 0] = 0)

- Multiplexing Ratio (M[1:0]=0)

- Frame Rate (FR[1:0]=”75Hz”)

- Power Down (PD = 1)

- Dual Partial Display Disabled (PE=0)

- VOP=0

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