I²C bus selection

STV6414A

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3

I²C bus selection

Data transfers follow the usual I²C format; that is, after the start condition (S), a 7-bit slave

address is sent, followed by an eight-bit data direction bit (W). An 8-bit sub-address is sent

to select a register, followed by an 8-bit data word to be included in the register. The IC’s I²C

bus decoder enables the automatic incrementation mode in write mode.

The circuit operates at clock frequencies of up to 400 kHz.

3.1

I²C bus addresses

Write Address: 1001 0110 = 96(hex), Read Address: 1001 0111 = 97(hex)

Table 14.

String format

Write only mode (S = Start condition, P = Stop condition, A = Acknowledge)

S

SLAVE ADDRESS

0

A

SUB-ADDRESS

A

DATA

A

P

Table 15.

Read only mode

S

SLAVE ADDRESS

1

A

DATA

A

P

Table 16.

Slave address

Address

A6

A5

A4

A3

A2

A1

A0

Value

1

0

0

1

0

1

X

Table 17.

Auto increment mode

S

SLAVE ADDRESS

0

A

SUB-ADDRESS

A

DATA0

A

DATA1

A

....

DATAn

A

P

Sub-Address

Sub-Address +1

Sub-Address + N

Table 18.

Input signal summary (write mode)

Reg add

(hex)

Data

d7

d6

d5

d4

d3

d2

d1

d0

Audio

00h

TV Stereo

Mono

TV 0/6dB

TV Volume-62dB to 0dB - 2dB steps

Soft

Volume

Mode

01h

VCR Stereo

Mono

Not Used

(See Note)

VCR Audio

Switch Control

CINCH

Audio

Gain

TV/CINCH Audio Switch Control

Video