STW5098T datasheet(20/86 Pages) STMICROELECTRONICS

20 / 86 page

STw5098

Functional description

19/85

4.4

Power up

STw5098 internal blocks can individually be switched on and off according to the user

needs. A general power-up bit is present at bit 7 of CR0. The output drivers should always

be powered up after the general power up. See the following drawing to select the needed

block for the desired function. A fast-settling function is activated to quickly charge external

capacitors when the device is switched on (CAPLS, CAPLINEIN and CAPMIC).

Figure 3.

Power up block diagram: example shown for one entity

4.5

Master clock

Master clock is applied to both entities. The master clock pin (AMCK) accepts any frequency

from 4 MHz to 32 MHz. The 4-32 MHz range is divided in sub-ranges that have to be

programmed in bits CKRANGE in CR30. The jitter and spectral properties of this clock have

a direct impact on the DAC and ADC performance because it is used to directly or by integer

division drive the continuous-time to sampled-time interfaces.

POWERUP

ENANA

STw5098

ENMIXL

ENHPVCM

ENHPL

ENLS

ENHPR

ENMICR

ENMICL

ENLINR

ENLINL

ENOSC

ENADCR

ENADCL

ENDACR

ENDACL

AUDIO I/F

ENLOL

ENLOR

ENHSD

ENPLL

DAMAST ENDAOCK

ADMAST ENADOCK

MBIAS

ENAMCK

ENDACKGEN

ENADCKGEN

ENOSC=1

ENOSC=0

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