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VS6735 数据表(PDF) 2 Page - STMicroelectronics |
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VS6735 数据表(HTML) 2 Page - STMicroelectronics |
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2 / 5 page ![]() Overview VS6725/VS6735 2/5 1 Overview Figure 3. System diagram Figure 1. VS6725 application diagram Figure 2. VS6735 application diagram SCL SDA CLK CE D[7:0] HSYNC PCLK FSO AVDD AGND VDD DGND 1152 x 864 Column ADC X Decoder Line SRAM ISP MCU PLL and Clock Management Power Mgmt Power-On Reset 2Mpixel VS6725 VSYNC} Pixel array SCL SDA CLK CE FSO AVDD AGND VDD DGND 1152 x 864 Column ADC X Decoder Line SRAM ISP MCU PLL and Clock Management Power Mgmt Power-On Reset 2 Mpixel VS6735 MIPI CSI-2 Pixel array AVDD GND SCL SDA CE 8 GND DIO[7:0] CLK PCLK HSYNC VSYNC FSO DVDD Baseband 2.8V 1.8V or Flashgun driver / controller External clock 2.8V 2 4.7KR DVDD or application processor VS6735 MIPI CSI-2 VS6725 4 VS6735 MIPI CSI-2 |
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