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STP5NB40FP 数据表(PDF) 1 Page - STMicroelectronics |
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STP5NB40FP 数据表(HTML) 1 Page - STMicroelectronics |
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1 / 7 page ![]() STP5NB40 STP5NB40FP N - CHANNEL ENHANCEMENT MODE PowerMESH ™ MOSFET PRELIMINARY DATA s TYPICAL RDS(on) = 1.47 Ω s 100% AVALANCHE TESTED s VERY LOW INTRINSIC CAPACITANCES s GATE CHARGE MINIMIZED s EXTREMELY HIGH dv/dt CAPABILITY DESCRIPTION Using the latest high voltage MESH OVERLAY ™ process, SGS-Thomson has designed an advanced family of Power MOSFETs with outstanding performance. The new patent pending strip layout coupled with the Company’s proprietary edge termination structure, gives the lowest RDS(on) per area, exceptional avalanche and dv/dt capabilities and unrivalled gate charge and switching characteristics. APPLICATIONS s HIGH CURRENT, HIGH SPEED SWITCHING s SWITCH MODE POWER SUPPLIES (SMPS) s DC-AC CONVERTERS FOR WELDING EQUIPMENT AND UNINTERRUPTIBLE POWER SUPPLIES AND MOTOR DRIVE This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Uni t STP5NB40 STP5NB40FP VDS Drain-source Volt age (VGS =0) 400 V VDGR Drain- gate Voltage (RGS =20 k Ω) 400 V VGS Gat e-source Voltage ± 30 V ID Drain Current (continuous) at Tc =25 o C4.7 3.1 A ID Drain Current (continuous) at Tc =100 oC3 2 A IDM( •) Drain Current (pulsed) 19 19 A Ptot Tot al Dissipation at Tc =25 oC80 35 W Derating F act or 0.64 0. 28 W/ oC dv/dt(1) Peak Diode Recovery voltage slope 4.5 4.5 V/ ns VISO Insulat ion Withstand Volt age (DC) 2000 V Tstg Storage T emperat ure -65 to 150 oC Tj Max. O perating Junction Temperature 150 oC ( •) Pulse width limited by safe operating area (1)ISD ≤ 5A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS,Tj ≤ TJMAX October 1997 1 2 3 TO-220 TO-220FP 1 2 3 TYPE VDSS RDS(on) ID STP5NB40 STP5NB40FP 400 V 400 V <1.8 Ω <1.8 Ω 4.7 A 3.1 A 1/7 |
类似零件编号 - STP5NB40FP |
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类似说明 - STP5NB40FP |
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