ABSOLUTE MAXIMUM RATINGS

(1)

DISSIPATION RATINGS

RECOMMENDED OPERATING CONDITIONS

THS7375

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PRODUCT

PACKAGE-LEAD

TRANSPORT MEDIA, QUANTITY

THS7375IPW

Rails, 90

TSSOP-14

Pb-Free, Green

THS7375IPWR

Tape and Reel, 2000

(1)

For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2)

These packages conform to Lead (Pb)-free and green manufacturing specifications. Additional details including specific material

contentcan be accessed at www.ti.com/leadfree.

GREEN: TI defines Green to mean Lead (Pb)-Free and in addition, uses less package materials that do not contain halogens, including

bromine (Br), or antimony (Sb) above 0.1% of total product weight. N/A: Not yet available Lead (Pb)-Free; for estimated conversion

dates, go to www.ti.com/leadfree. Pb-FREE: TI defines Lead (Pb)-Free to mean RoHS compatible, including a lead concentration that

does not exceed 0.1% of total product weight, and, if designed to be soldered, suitable for use in specified lead-free soldering

processes.

Over operating free-air temperature range unless otherwise noted.

THS7375

UNIT

5.5

V

V

±90

mA

Continuous power dissipation

See Dissipation Ratings Table

+150

°C

+125

°C

–65 to +150

°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

+300

°C

Human body model (HBM)

2000

V

ESD ratings

Charged device model (CDM)

1000

V

Machine model

200

V

(1)

Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

(2)

The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process.

(3)

The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this

temperature may result in reduced reliability and/or lifetime of the device.

θ

JC

θ

JA

PACKAGE

(°C/W)

(°C/W)

TSSOP-14 (PW)

35

870 mW

348 mW

(1)

Power rating is determined with a junction temperature of +125°C. This is the point where performance starts to degrade and long-term

reliability starts to be reduced. Thermal management of the final PCB should strive to keep the junction temperature at or below +125°C

for best performance and reliability.

(2)

These data were taken with the JEDEC High-K test printed circuit board (PCB). For the JEDEC low-K test PCB, the

θ

MIN

NOM

MAX

UNIT

3

5

V

–40

+85

°C

2

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