STPCATLAS datasheet(3/111 Pages) STMICROELECTRONICS

3 / 111 page

STPC

® ATLAS

Issue 1.0 - July 24, 2002

3/111

TFT Interface

Programmable panel size up to 1024 by 1024

pixels.

Support for VGA and SVGA active matrix

TFT flat panels with 9, 12, 18-bit interface (1

pixel per clock).

Support for XGA and SXGA active matrix

TFT flat panels with 2 x 9-bit interface (2

pixels per clock).

Programmable image positionning.

Programmable blank space insertion in text

mode.

Programmable horizontal and vertical image

expansion in graphic mode.

One fully programmable PWM (Pulse Width

Modulator) signals to adjust the flat panel

brightness and contrast.

Supports PanelLink

high speed serial

transmitter externally for high resolution

panel interface.

PCI Controller

Compatible with PCI 2.1 specification.

Integrated PCI arbitration interface. Up to 3

masters can connect directly. External logic

allows for greater than 3 masters.

Translation of PCI cycles to ISA bus.

Translation of ISA master initiated cycle to

PCI.

Support for burst read/write from PCI master.

PCI clock is 1/2, 1/3 or 1/4 Host bus clock.

ISA master/slave

Generates the ISA clock from either

14.318MHz oscillator clock or PCI clock

Supports programmable extra wait state for

ISA cycles

Supports I/O recovery time for back to back

I/O cycles.

Fast Gate A20 and Fast reset.

Supports the single ROM that C, D, or E.

blocks shares with F block BIOS ROM.

Supports flash ROM.

Supports ISA hidden refresh.

Buffered DMA & ISA master cycles to reduce

bandwidth utilization of the PCI and Host

bus.

Local Bus interface

Multiplexed with ISA/DMA interface.

Low latency asynchronous bus

16-bit data bus with word steering capability.

Programmable timing (Host clock granularity)

4 Programmable Flash Chip Select.

8 Programmable I/O Chip Select.

I/O device timing (setup & recovery time)

programmable

Supports 32-bit Flash burst.

2-level hardware key protection for Flash boot

block protection.

Supports 2 banks of 32MB flash devices with

boot block shadowed to 0x000F0000.

Reallocatable Memory space Windows

EIDE Interface

Supports PIO

Transfer Rates to 22 MBytes/sec

Supports up to 4 IDE devices

Concurrent channel operation (PIO modes) -

4 x 32-Bit Buffer FIFOs per channel

Support for PIO mode 3 & 4.

Individual drive timing for all four IDE devices

Supports both legacy & native IDE modes

Supports hard drives larger than 528MB

Support for CD-ROM and tape peripherals

Backward compatibility with IDE (ATA-1).

Integrated Peripheral Controller

2X8237/AT compatible 7-channel DMA

controller.

2X8259/AT compatible interrupt Controller.

16 interrupt inputs - ISA and PCI.

Three 8254 compatible Timer/Counters.

Co-processor error support logic.

Supports external RTC (Not in Local Bus

Mode).

STPCATLAS 数据表(PDF) 3 Page - STMicroelectronics

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