STPCD0166BTC3 datasheet(17/48 Pages) STMICROELECTRONICS

17 / 48 page

PIN DESCRIPTION

Issue 1.7 - February 8, 2000

17/48

LA[22]/SCS1#

Unlatched Address (ISA) / Sec-

ondary Chip Select (IDE) This pin has two func-

tions, depending on whether the ISA bus is active

or the IDE bus is active.

When the ISA bus is active, this pin is ISA bus un-

latched address bit 22 for 16-bit devices. When

ISA bus is accessed by any cycle initiated from

PCI bus, this pin is in output mode. When an ISA

bus master owns the bus, this pin is in input mode.

When the IDE bus is active, this signal is used as

the active high secondary slave IDE chip select

signal. This signal is to be externally ANDed with

the ISAOE# signal before driving the IDE devices

to guarantee it is active only when ISA bus is idle.

LA[21]/PCS3#

Unlatched Address (ISA) / Primary

Chip Select (IDE). This pin has two functions, de-

pending on whether the ISA bus is active or the

IDE bus is active.

When the ISA bus is active, this pin is ISA Bus un-

latched address bit 21 for 16-bit devices. When

ISA bus is accessed by any cycle initiated from

PCI bus, this pin is in output mode. When an ISA

bus master owns the bus, this pin is in input mode.

When the IDE bus is active, this signas is used as

the active high primary slave IDE chip select sig-

nal. This signal is to be externally NANDed with

the ISAOE# signal before driving the IDE devices

to guarantee it is active only when ISA bus is idle.

LA[20]/PCS1#

Unlatched Address (ISA) / Primary

Chip Select (IDE). This pin has two functions, de-

pending on whether the ISA bus is active or the

IDE bus is active.

When the ISA bus is active, this pin is ISA Bus un-

latched address bit 20 for 16-bit devices. When

the ISA bus is accessed by any cycle initiated from

PCI bus, this pin is in output mode. When an ISA

bus master owns the bus, this pin is in input mode.

When the IDE bus is active, this signals is used as

the active high primary slave IDE chip select sig-

nal. This signal is to be externally NANDed with

the ISAOE# signal before driving the IDE devices

to guarantee it is active only when ISA bus is idle.

LA[19:17]/DA[2:0]

Unlatched Address (ISA) / Ad-

dress (IDE). These pins are multi-function pins.

They are used as the ISA bus unlatched address

bits [19:17] for ISA bus or the three address bits

for the IDE bus devices.

When used by the ISA bus, these pins are ISA bus

unlatched address bits 19-17 on 16-bit devices.

When the ISA bus is accessed by any cycle initiat-

ed from the PCI bus, these pins are in output

mode. When an ISA bus master owns the bus,

these pins are tristated.

For IDE devices, these signals are used as the

DA[2:0] and are connected directly or through a

buffer to DA[2:0] of the IDE devices. If the toggling

of signals are to be masked during ISA bus cycles,

they can be externally ORed before being con-

nected to the IDE devices.

SA[19:8]/DD[11:0]

Unlatched Address (ISA) /

Data Bus (IDE). These are multifunction pins.

When the ISA bus is active, they are used as the

ISA bus system address bits 19-8. When the IDE

bus is active, they serve as IDE signals DD[11:0].

These pins are used as an input when an ISA bus

master owns the bus and are outputs at all other

times.

IDE devices are connected to SA[19:8] directly

and the ISA bus is connected to these pins

through two LS245 transceivers. The transceiver

OEs are connected to ISAOE# and the DIR is con-

nected to MASTER#. The transceiver bus signals

are connected to the CPC and IDE DD busses

and B bus signals are connected to ISA SA bus.

DD[15:12]

Databus (IDE). The high 4 bits of the

IDE databus are combined with several of the X-

bus lines. Refer to the following section for X-bus

pins for further information.

SA[7:0]

ISA Bus address bits [7:0]. These are the

8 low bits of the system address bus of ISA on 8-

bit slot. These pins are used as an input when an

ISA bus master owns the bus and are outputs at

all other times.

SD[15:0]

I/O Data Bus (ISA). These pins are the

external databus to the ISA bus.

2.2.7.

ISA/IDE COMBINED CONTROL

IOCHRDY/DIORDY

Channel Ready (ISA) / Busy /

Ready (IDE). This is a multi-function pin. When

the ISA bus is active, this pin is IOCHRDY. When

the IDE bus is active, this serves as IDE signal DI-

ORDY.

IOCHRDY is the I/O channel ready signal of the

ISA bus and is driven as an output in response to

an ISA master cycle targeted to the host bus or an

internal register of the STPC Client. The STPC

Client monitors this signal as an input when per-

forming an ISA cycle on behalf of the host CPU,

DMA master or refresh.

ISA masters which do not monitor IOCHRDY are

not guaranteed to work with the STPC Client since

the access to the system memory can be consid-

erably delayed due to CRT refresh or a write back

cycle.

STPCD0166BTC3 数据表(PDF) 17 Page - STMicroelectronics

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STPCD0166BTC3 数据表(PDF) 17 Page - STMicroelectronics

STPCD0166BTC3 数据表(HTML) 17 Page - STMicroelectronics

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