STPIC44L02 datasheet(2/21 Pages) STMICROELECTRONICS

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STPIC44L02

2/21

output buffer that puts SDO in a high impedance

state and clears and reenables the fault register.

The STPIC44L02 was designed to allow the serial

input interfaces of multiple devices to be cascated

together to simplify the serial interface of the

controller. Serial input data flows through the

device and is transferred out SDO following the

fault data in cascaded configurations.

For parallel operation, data is transferred directly

from the parallel input interface IN0-IN3 to the

respective GATE(0-3) output asynchronously.

SCLK or CS is not required for parallel control. A 1

on the parallel input turns the respective channel

on, where as a 0 turns it off. Note that either the

serial input interface or the parallel input interface

can enable a channel. Under parallel operation,

fault data must still be collected through the serial

data interface.

The predriver monitors the drain voltage for each

channel to detect shorted load or open load fault

conditions, in the on and off state respectively.

These devices offer the option of using an

internally generated fault reference voltage or an

externally supplied fault reference voltage through

VCOMP for fault detection. The internal fault

reference is selected by connecting VCOMPEN to

GND and the external reference is selected by

connecting VCOMPEN to VCC. The drain voltage is

compared to the fault reference when the channel

is turned on to detect shorted load conditions and

when the channel is off to detect open load

conditions.

fault

occurs,

the

channel

transitates into a low duty cycle, pulse width

modulated (PWM) signal as long as the fault is

present. Shorted load fault conditions must be

present for at least the shorted load deglicth time,

t(STBDG), to be flagged as a fault. A fault flag is

sent to the control device as well as the serial fault

operation is presented in the device operation

section of this datasheet.

The device provides protection from over battery

voltage and under battery voltage conditions

irrespective of the state of the output channels.

When the battery voltage is greater than the

overvoltage

threshold

less

than

the

undervotlage threshold, all channels are disabled

and a fault flag is generated. Battery voltage faults

are not reported in the serial fault data. The

outputs return to normal operation once the

battery voltage fault has been corrected. When an

over

battery/under

battery

voltage

condition

occurs, the device reports the battery fault, but

disables fault reporting for open and shorted load

conditions. Fault reporting for open and shorted

load conditions are reenabled after the battery

fault condition has been corrected.

This device provides inductive transient protection

on all channels. The drain voltage is clamped to

protect the FET. The clamp voltage is defined by

the sum of VCC and turn on voltage of the external

FET. The predriver also provides a gate to source

voltage (VGS) clamp to protect the gate source

terminals of the power FET from exceeding their

rated voltages. An external active low RESET is

provided to clear all register and flags in the

device. GATE(0-3) outputs are disabled after

RESET has been pulled low.

The device provide pull-down resistors on all

inputs except CS and RESET. A pull-up resistor is

used on CS and RESET.

ORDERING CODES

Type

Package

Comments

STPIC44L02PTR

SSOP24 (Tape & Reel)

1350 parts per reel

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