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STPCE1HEBC 数据表(PDF) 13 Page - STMicroelectronics

部件名 STPCE1HEBC
功能描述  X86 Core General Purpose PC Compatible System - on - Chip
PDF  87 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STPCE1HEBC 数据表(HTML) 13 Page - STMicroelectronics

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PIN DESCRIPTION
Release 1.3 - January 29, 2002
13/87
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
ISA_CLK
O
BT8TRP_TC
ISA Clock Output - Multiplexer Select
Line For IPC
1
ISA_CLK2X
O
BT8TRP_TC
ISA Clock x2 Output - Multiplexer Select
Line For IPC
1
OSC14M
O
BD8STRP_FT
Buffered 14MHz clock
1
LA[23:17]
O
BD8STRUP_FT
Unlatched Address
7
SA[19:0]
I/O
BD8STRUP_FT
Latched Address
20
SD[15:0]
I/O
BD8STRP_FT
Data Bus
16
ALE
O
BD4STRP_FT
Address Latch Enable
1
MEMR#, MEMW#
I/O
BD8STRUP_FT
Memory Read and Memory Write
2
SMEMR#, SMEMW#
O
BD8STRUP_FT
System Memory Read and Memory
Write
2
IOR#, IOW#
I/O
BD8STRUP_FT
I/O Read and Write
2
MCS16#, IOCS16#
I
BD4STRUP_FT
Memory/IO Chip Select16
2
BHE#
O
BD8STRUP_FT
System Bus High Enable
1
ZWS#
I
BD4STRP_FT
Zero Wait State
1
REF#
O
BD8STRP_FT
Refresh Cycle.
1
MASTER#
I
BD4STRUP_FT
Add On Card Owns Bus
1
AEN
O
BD8STRUP_FT
Address Enable
1
IOCHCK#
I
BD4STRUP_FT
I/O Channel Check.
1
IOCHRDY
I/O
BD8STRUP_FT
I/O Channel Ready (ISA) - Busy/Ready
(IDE)
1
ISAOE#
O
BD4STRP_FT
ISA/IDE Selection
1
GPIOCS#
I/O
BD4STRP_FT
General Purpose Chip Select
1
IRQ_MUX[3:0]
I
BD4STRP_FT
Time-Multiplexed Interrupt Request
4
DREQ_MUX[1:0]
I
BD4STRP_FT
Time-Multiplexed DMA Request
2
DACK_ENC[2:0]
O
BD4STRP_FT
Encoded DMA Acknowledge
3
TC
O
BD4STRP_FT
ISA Terminal Count
1
RTCAS
O
BD4STRP_FT
Real Time Clock Address Strobe
1
RMRTCCS#
I/O
BD4STRP_FT
ROM/RTC Chip Select
1
KBCS#
I/O
BD4STRP_FT
Keyboard Chip Select
1
RTCRW#
I/O
BD4STRP_FT
RTC Read/Write
1
RTCDS#
I/O
BD4STRP_FT
RTC Data Strobe
1
LOCAL BUS
PA[23:20], [15], [8], [3:0]
O
BD4STRP_FT
Address Bus
10
PA[19:16], [14:12],[7:4]
O
BD8STRUP_FT
Address Bus
11
PA[11]
O
BD8STRP_FT
Address Bus
1
PA[10:9]
O
BD4STRUP_FT
Address Bus
2
PD[15:0]
I/O
BD8STRP_FT
Data Bus
16
PRD1#,PRD0#
O
BD4STRUP_FT
Peripheral Read Control
2
PWR1#
O
BD8STRUP_FT
Peripheral Write Control
1
PWR0#
O
BD4STRUP_FT
Peripheral Write Control
1
PRDY
I
BD8STRUP_FT
Data Ready
1
FCS1#, FCS0#
O
BD4STRP_FT
Flash Chip Select
2
IOCS#[3]
O
BD4STRP_FT
I/O Chip Select
1
IOCS#[2:0]
O
BD8STRUP_FT
I/O Chip Select
3
Table 2-2. Definition of Signal Pins
Signal Name
Dir
Buffer Type2
Description
Qty
Note1: These pins must be connected to the 2.5 V power supply. They must not be connected to the 3.3V supply.
Note2: See Table 2-3 for buffer type descriptions.



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