STPCI0180BTI3 datasheet(4/55 Pages) STMICROELECTRONICS

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GENERAL DESCRIPTION

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Issue 1.1

1 GENERAL DESCRIPTION

At the heart of the STPC Industrial is an

advanced 64-bit processor block, dubbed the

5ST86. The 5ST86 includes a powerful x86

processor core along with a 64-bit DRAM

controller, advanced 64-bit accelerated graphics

and video controller, a high speed PCI local-bus

controller and Industry standard PC chip set

functions (Interrupt controller, DMA Controller,

Interval timer and ISA bus).

The STPC Industrial has in addition to the 5ST86

a TFT output, a Local Bus interface, PC Card and

super I/O features.

The STPC Industrial makes use of a tightly

coupled Unified Memory Architecture (UMA),

where the same memory array is used for CPU

main memory and graphics frame-buffer. This

means a reduction in total system memory for

system performances that are equal to that of a

comparable frame buffer and system memory

based system, and generally much better, due to

the

higher

memory

bandwidth

allowed

attaching the graphics engine directly to the 64-bit

processor host interface running at the speed of

the processor bus rather than the traditional PCI

bus.

The 64-bit wide memory array provides the

system with 320MB/s peak bandwidth, double

that of an equivalent system using 32 bits. This

allows for higher resolution screens and greater

color depth. The processor bus runs at 66Mhz

further increasing “standard” bandwidth by at

least a factor of two.

The ‘standard’ PC chipset

functions (DMA,

interrupt controller, timers, power management

logic) are integrated together with the x86

processor core; additional functions such as

communication ports are accessed by the STPC

Industrial via an internal ISA bus.

The PCI bus is the main data communication link

to the STPC Industrial chip. The STPC Industrial

translates appropriate host bus I/O and Memory

cycles onto the PCI bus. It also supports the

generation of Configuration cycles on the PCI

bus. The STPC Industrial, as a PCI bus agent

(host bridge class), fully complies with PCI

specification 2.1. The chip-set also implements

the PCI mandatory header registers in Type 0 PCI

configuration space for easy porting of PCI aware

system

BIOS.

The

device contains a

PCI

arbitration function for three external PCI devices.

Graphics functions are controlled through the on-

chip SVGA controller and the monitor display is

produced through the 2D graphics display engine.

This Graphics Engine is tuned to work with the

host CPU to provide a balanced graphics system

with a low silicon area cost. It performs limited

graphics

drawing

operations

which

include

hardware acceleration of text, bitblts, transparent

blts and fills. The results of these operations

change the contents of the on-screen or off-

screen frame buffer areas of DRAM memory. The

frame buffer can occupy a space up to 4 Mbytes

anywhere in the physical main memory.

The maximum graphics resolution supported is

1280x1024 in 65536 colours at 75Hz refresh rate

and is VGA and SVGA compatible. Horizontal

timing fields are VGA compatible while the vertical

fields are extended by one bit to accommodate

above display resolution.

To generate the TFT output, the STPC Industrial

extracts the digital video stream before the

RAMDAC and reformats it to the TFT format. The

height

and

width

the

flat

panel

are

programmable through configuration registers up

to a size of 1024 by 1024.

By default, lower resolution images cover only a

part of the larger TFT panel. The STPC Industrial

allows to expand the image vertically

and

horizontally

text

mode

inserting

programmable blank pixels. It allows expantion of

the image vertically and horizontally in graphics

mode by replicating pixels. The replication of J

times

every

pixel

independently

programmable

in the vertical and horizontal

directions.

PanelLinkTM is

proprietary

interconnect

protocol defined by Silicon Image, Inc. It consists

of a transmitter that takes parallel video/graphics

data from the host LCD graphics controller and

transmits it serially at high speed to the receiver

which controls the TFT panel. The TFT interface

is designed to support the connection of this

control signal to the PanelLinkTM transmitter.

The STPC Industrial CARDBUS / PCMCIA

controller has been specifically designed to

provide the interface with PC-Cards which contain

additional memory or I/O and provides an

ExCATM implementation to PCMCIA 2.0 / JEIDA

4.1 standards.

The power management control facilities include

socket power control, insertion/removal capability,

power saving with Windows inactivity, NCS

controlled Chip Power Down, together with further

controls for 3.3v suspend with Modem Ring

Resume Detection.

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