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STPC4EDBI 数据表(PDF) 68 Page - STMicroelectronics |
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STPC4EDBI 数据表(HTML) 68 Page - STMicroelectronics |
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68 / 93 page  DESIGN GUIDELINES 68/93 Release 1.5 - January 29, 2002 For other implementations like 32-bit SDRAM devices, refers to the SDRAM controller signal multiplexing and address mapping described in the following Table 6-4 and Table 6-5. 6.3.4. PCI BUS The PCI bus is always active and the following control signals must be pulled-up to 3.3V or 5V through 2K2 resistors even if this bus is not connected to an external device: FRAME#, TRDY#, IRDY#, STOP#, DEVSEL#, LOCK#, SERR#, PCI_REQ#[2:0]. PCI_CLKO must be connected to PCI_CLKI through a 10 to 33 Ohms resistor. Figure 6-7 shows a typical implementation. For more information on layout constraints, go to the place and route recommendations section. Table 6-4. DIMM Pinout SDRAM Density 16 Mbit 64/128 Mbit 64/128 Mbit STPC I/F Internal Banks 2 Banks 2 Banks 4 Banks DIMM Pin Number ... MA[10:0] MA[10:0] MA[10:0] MA[10:0] 123 - MA11 MA11 CS2# (MA11) 126 - MA12 - CS3# (MA12) 39 - - BA1 (MA12) CS3# (BA1) 122 BA0 (MA11) BA0 (MA13) BA0 (MA13) BA0 Table 6-5. Address Mapping Address Mapping: 16 Mbit - 2 internal banks STPC I/F BA0 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS Address A11 A22 A21 A2 A19 A18 A17 A16 A15 A14 A13 A12 CAS Address A11 0 A24 A23 A10 A9 A8 A7 A6 A5 A4 A3 Address Mapping: 64/128 Mbit - 2 internal banks STPC I/F BA0 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS Address A11 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 CAS Address A11 0 0 0 A26 A25 A10 A9A8A7A6A5A4A3 Address Mapping: 64/128 Mbit - 4 internal banks STPC I/F BA0 BA1 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 RAS Address A11 A12 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 CAS Address A11 A12 0 0 A26 A25 A10 A9 A8 A7 A6 A5 A4 A3 Figure 6-7. Typical PCI clock routing PCICLKI PCICLKO PCICLKA PCICLKB PCICLKC 0 - 22 10 - 33 Device A Device B Device C 0 - 33pF |
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