 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
STPC0310BTC3 数据表(PDF) 32 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STPC0310BTC3 数据表(HTML) 32 Page - STMicroelectronics |
|
|
32 / 51 page  ELECTRICAL SPECIFICATIONS 32/51 Issue 1.2 Figure 4-1 Drive Level and Measurement Points for Switching Characteristics Figure 4-2 CLK Timing Measurement Points Note; The above timings are generic timings and are not specific to the interfaces defined below CLK: VRef VILD VIHD Tx LEGEND: A - Maximum Output Delay Specification B - Minimum Output Delay Specification C - Minimum Input Setup Specification D - Minimum Input Hold Specification VRef Valid Valid Valid OUTPUTS: INPUTS: Output n Outp ut n+1 Input MAX MIN A B CD VRef VILD VIHD CLK T5 T4 T3 VRef VIL (MAX) VIH (MIN) T2 T1 LEGEND: T1 - One Clock Cycle T2 - Minimum Time at VIH T3 - Minimum Time at VIL T4 - Clock Fall Time T5 - Clock Rise Time NOTE; All sIgnals are sampled on the rising edge of the CLK. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
