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STPCC01 数据表(PDF) 33 Page - STMicroelectronics

部件名 STPCC01
功能描述  PC Compatible Embeded Microprocessor
PDF  51 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STPCC01 数据表(HTML) 33 Page - STMicroelectronics

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ELECTRICAL SPECIFICATIONS
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Issue 1.2
4.5.1 AC Timing parameters
Table 4-4. PCI Bus AC Timing
Name
Parameter
Min
Max
Unit
t1
PCI_CLKI to AD[31:0] valid
2
11
ns
t2
PCI_CLKI to FRAME# valid
2
11
ns
t3
PCI_CLKI to CBE#[3:0] valid
2
11
ns
t4
PCI_CLKI to PAR valid
2
11
ns
t5
PCI_CLKI to TRDY# valid
2
11
ns
T6
PCI_CLKI to IRDY# valid
2
11
ns
T7
PCI_CLKI to STOP# valid
2
11
ns
T8
PCI_CLKI to DEVSEL# valid
2
11
ns
T9
PCI_CLKI to PCI_GNT# valid
2
12
ns
t10
AD[31:0] bus setup to PCI_CLKI
7
ns
t11
AD[31:0] bus hold from PCI_CLKI
0
ns
t12
PCI_REQ#[2:0] setup to PCI_CLKI
7
ns
t13
PCI_REQ#[2:0] hold from PCI_CLKI
4
ns
t14
CBE#[3:0] setup to PCI_CLKI
7
ns
t15
CBE#[3:0] hold to PCI_CLKI
0
ns
t16
IRDY# setup to PCI_CLKI
7
ns
t17
IRDY# hold to PCI_CLKI
0
ns
t18
FRAME# setup to PCI_CLKI
7
ns
t19
FRAME# hold from PCI_CLKI
0
ns
Table 4-5. DRAM Bus AC Timing
Name
Parameter
Min
Max
Unit
t22
HCLK to RAS#[3:0] valid
19
ns
t23
HCLK to CAS#[7:0] bus valid
19
ns
t24
HCLK to MA[11:0] bus valid
19
ns
t25
HCLK to MWE# valid
17
ns
t26
HCLK to MD[63:0] bus valid
20
ns
t27
MD[63:0] Generic setup
13
ns
t28
GCLK2X to RAS#[3:0] valid
19
ns
t29
GCLK2X to CAS#[7:0] valid
19
ns
t30
GCLK2X to MA[11:0] bus valid
19
ns
t31
GCLK2X to MWE# valid
17
ns
t32
GCLK2X to MD[63:0] bus valid
20
ns
t33
MD[63:0] Generic hold
0
ns
Table 4-6. IDE Bus AC Timing
Name
Parameter
Min
Max
Unit
t20
DD[15:0] setup to PIOR#/SIOR# falling
15
ns
t21
DD[15:0} hold to PIOR#/SIOR# falling
0
ns



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