L5986 datasheet(19/39 Pages) STMICROELECTRONICS

19 / 39 page

L5986 - L5986A

Application information

19/39

minimize the dc error on regulated output voltage; finally to place other poles far away the

zero dB frequency.

If the equivalent series resistance (ESR) of the output capacitor introduces a zero with a

frequency higher than the desired bandwidth (that is: 2

π∗ESR∗COUT<1/BW), the type III

compensation network is needed. Multi Layer Ceramic capacitors (MLCC) have very low

ESR (<1 m

Ω), with very high frequency zero, so type III network is adopted to compensate

the loop.

In Figure 9 the type III compensation network is shown. This network introduces two zeros

(fZ1, fZ2) and three poles (fP0, fP1, fP2). They expression are:

Equation 16

Equation 17

Figure 9.

Type III compensation network

In Figure 10 the Bode diagram of the PWM and LC filter transfer function (GPW0 · GLC(f))

and the open loop gain (GLOOP(f) = GPW0 · GLC(f) · GTYPEIII(f)) are drawn.

π C

()

⋅⋅

------------------------------------------------

π R

⋅⋅

------------------------------

π R

⋅⋅

------------------------------

π R

⋅

--------------------

⋅⋅

--------------------------------------------

L5986 数据表(PDF) 19 Page - STMicroelectronics

L5986 数据表(HTML) 19 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

数据表下载