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VIPER28LN 数据表(PDF) 22 Page - STMicroelectronics

部件名 VIPER28LN
功能描述  Off-line high voltage converters
PDF  29 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

VIPER28LN 数据表(HTML) 22 Page - STMicroelectronics

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Operation descriptions
VIPER28
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At the same time an internal current generator starts to charge the feedback capacitor
(CFB) and when the feedback voltage reaches the VFBolp threshold, the converter is turned
off and the start up phase is activated with reduced value of Icharge to 0.6 mA.
During the first start up phase of the converter, after the soft-start up time (typical value is
8.5 ms) the output voltage could force the feedback pin voltage to rise up to the VFBolp
threshold that switches off the converter itself.
To avoid this event, the appropriate feedback network has to be selected according to the
output load. More the network feedback fixes the compensation loop stability. The Figure 24
on page 23 and Figure 25 on page 23 show the two different feedback networks.
The time from the overload detection (VFB = VFBlin) to the device shutdown
(VFB = VFBolp) can be calculated by CFB value (see Figure 24 on page 23 and Figure 25),
using the formula:
Equation 5
In the Figure 24, the capacitor connected to FB pin (CFB) is used as part of the circuit to
compensate the feedback loop but also as element to delay the OLP shut down owing to the
time needed to charge the capacitor (see Equation 5).
After the start up time, 8.5 ms typ value, during which the feedback voltage is fixed at VFBlin,
the output capacitor could not be at its nominal value and the controller interpreters this
situation as an overload condition. In this case, the OLP delay helps to avoid an incorrect
device shut down during the start up face.
Owing to the above considerations, the OLP delay time must be long enough to by-pass the
initial output voltage transient and check the overload condition only when the output voltage
is in steady state. The output transient time depends from the value of the output capacitor
and from the load.
When the value of the CFB capacitor calculated for the loop stability is too low and cannot
ensure enough OLP delay, an alternative compensation network can be used and it is
showed in Figure 25 on page 23.
Using this alternative compensation network, two poles (fPFB, fPFB1) and one zero (fZFB) are
introduced by the capacitors CFB and CFB1 and the resistor RFB1.
The capacitor CFB introduces a pole (fPFB) at higher frequency than fZB and fPFB1. This pole
is usually used to compensate the high frequency zero due to the ESR (Equivalent Series
Resistor) of the output capacitance of the fly-back converter.
The mathematical expressions of these poles and zero frequency, considering the scheme
in Figure 25 are reported by the equations below:
Equation 6
T
OLP
delay
C
FB
V
FBolp
V
FBlin
3
μA
----------------------------------------
×
=
1
FB
1
FB
ZFB
R
C
2
1
f
π
=



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