M41ST87Y_08 datasheet(39/48 Pages) STMICROELECTRONICS

部件名	M41ST87Y

功能描述	5.0 V and 3.3/3.0 V secure serial RTC and NVRAM supervisor with tamper detection and 128 bytes of clearable NVRAM

PDF	48 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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39 / 48 page

M41ST87Y, M41ST87W

Clock operation

39/48

Table 12.

trec definitions

Note:

All other control bits are undetermined.

trec bit (TR)

STOP bit (ST)

trec time

Units

Min

Max

98(1)

Default setting

200

2000

µs

Table 13.

Default values

Condition

OFIE

HT(1)

Out

AFE

Initial power-up

Subsequent power-up (with

battery backup)(2)(3)

⇑

⇓

⇑

Condition

ABE

SQWE

SQWOD

PFOD

Watchdog register(4)

Initial power-up

Subsequent power-up (with

battery backup)(2)(3)

⇑

⇓

Condition

32kE

THS

TEB1 and 2

TCM1 and 2

TPM1 and 2

TDS1 and 2

Initial power-up

1(5)

Subsequent power-up (with

battery backup)(2)

Condition

TCHI/TCLO1

and 2

CLR1

and 2

TIE1 and 2

CLRPW0

CLRPW1

CLR1EXT

and

CLR2EXT

Initial power-up

Subsequent power-up (with

battery backup)(2)

⇑

When TEBX is set to '1,' the HT bit will not be set on power-down (tamper time-stamp will have precedence).

UC = unchanged.

⇑ = V

CC rising; ⇓ = VCC falling.

WDS, BMB0-BMB4, RB0, RB1.

32 kHz output valid only on VCC.

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