Device description and operation

L6743, L6743Q

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5.1

High-impedance (HiZ) management

The driver is able to manage high-impedance state by keeping all MOSFETs in off state in

two different ways.

●

If the EN signal is pulled low, the device will keep all MOSFETs OFF careless of the

PWM status.

●

When EN is asserted, if the PWM signal remains in the HiZ window for a time longer

than the hold-off time, the device detects the HiZ condition so turning off all the

MOSFETs. The HiZ window is defined as the PWM voltage range comprised between

See Figure 4 for details about HiZ timings.

The implementation of the high-impedance state allows the controller that will be connected

to the driver to manage high-impedance state of its output, avoiding to produce negative

undershoot on the regulated voltage during the shut-down stage. Furthermore, different

power management states may be managed such as pre-bias start-up.

5.2

Preliminary OV protection

After VCC has overcome its UVLO threshold and while in HiZ, L6743, L6743Q activates the

Preliminary-OV protection.

The intent of this protection is to protect the load especially from high-side MOSFET failures

during the system start-up. In fact, VRM, and more in general PWM controllers, have a 12 V

bus compatible turn-on threshold and results to be non-operative if VCC is below that turn-

on thresholds (that results being in the range of about 10 V). In case of a high-side MOSFET

failure, the controller won’t recognize the over voltage until VCC = ~10 V (unless other

special features are implemented): but in that case the output voltage is already at the same

voltage (~10 V) and the load (CPU in most cases) already burnt.

L6743, L6743Q by-pass the PWM controller by latching on the low-side MOSFET in case

the HiZ window, the protection is reset and the control of the output voltage is transferred to

the controller connected to the PWM input.

Since the driver has its own UVLO threshold, a simple way to provide protection to the

output in all conditions when the device is OFF consists in supplying the controller through

short, the low-side MOSFET is driven with 5 V assuring a reliable protection of the load.

Preliminary OV is active after UVLO and while the driver is in HiZ state and it is disabled

after the first PWM transition. The controller will have to manage its output voltage from that

time on.