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VIPER17LN 数据表(PDF) 24 Page - STMicroelectronics |
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VIPER17LN 数据表(HTML) 24 Page - STMicroelectronics |
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24 / 33 page ![]() Operation descriptions VIPER17 24/33 7.11 Burst-mode operation at no load or very light load When the voltage on feedback pin falls down 50 mV below the burst mode threshold, VFBbm, power MOSFET is not more allowed to be switched on. It can be switched on again if the voltage on feedback pin exceeds VFBbm. The voltage on PWM comparator non inverting internal input, connected to feedback pin through a resistive voltage divider, is lower clamped to a certain value leading to a minimum value, of 90 mA (typ.) for the drain peak current. When the load decrease the feedback loop reacts lowering the feedback pin voltage. As the voltage goes 50 mV below VFBbm MOSFET stops switching. After the MOSFET stops, as a result of the feedback reaction to the energy delivery stop, the feedback pin voltage increases and exceeding VFBbm threshold MOSFET the power device start switching again. Figure 30 shows this behavior called burst mode. Systems alternates period of time where power MOSFET is switching to period of time where power MOSFET is not switching. The power delivered to output during switching periods exceeds the load power demands; the excess of power is balanced from not switching period where no power is processed. The advantage of burst mode operation is an average switching frequency much lower then the normal operation working frequency, up to some hundred of hertz, minimizing all frequency related losses. Figure 30. Burst mode timing diagram, light load management I DS VFBbm FB t t 50 mV hyster. Burst-mode Normal-mode Normal-mode t t 50 mV hyster. Burst-mode Burst-mode Normal-mode Normal-mode Normal-mode Normal-mode 100 |
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