MSC7118 datasheet(2/60 Pages) FREESCALE

2 / 60 page

MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7

Freescale Semiconductor

Table of Contents

Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.1

MAP-BGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . .4

1.2

Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .6

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.1

Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.2

Recommended Operating Conditions. . . . . . . . . . . . . .18

2.3

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .19

2.4

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .19

2.5

AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .39

3.1

Thermal Design Considerations . . . . . . . . . . . . . . . . . .39

3.2

Power Supply Design Considerations. . . . . . . . . . . . . .40

3.3

Estimated Power Usage Calculations. . . . . . . . . . . . . .47

3.4

Reset and Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

3.5

DDR Memory System Guidelines . . . . . . . . . . . . . . . . .52

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

List of Figures

Figure 1.

MSC7118 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2.

MSC7118 Molded Array Process-Ball Grid Array

(MAP-BGA), Top View . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3.

MSC7118 Molded Array Process-Ball Grid Array

(MAP-BGA), Bottom View . . . . . . . . . . . . . . . . . . . . . . 5

Figure 4.

Timing Diagram for a Reset Configuration Write . . . . 25

Figure 5.

DDR DRAM Input Timing Diagram . . . . . . . . . . . . . . 26

Figure 6.

DDR DRAM Output Timing Diagram . . . . . . . . . . . . . 27

Figure 7.

DDR DRAM AC Test Load . . . . . . . . . . . . . . . . . . . . . 28

Figure 8.

TDM Receive Signals. . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 9.

TDM Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 10. Read Timing Diagram, Single Data Strobe . . . . . . . . 31

Figure 11.

Read Timing Diagram, Double Data Strobe . . . . . . . . 31

Figure 12. Write Timing Diagram, Single Data Strobe. . . . . . . . . 32

Figure 13. Write Timing Diagram, Double Data Strobe . . . . . . . . 32

Figure 14. Host DMA Read Timing Diagram, HPCR[OAD] = 0 . . 33

Figure 15. Host DMA Write Timing Diagram, HPCR[OAD] = 0 . . 33

Figure 16. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 17. UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 18. UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 19. EE Pin Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 20. EVNT Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 21. GPI/GPO Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 22. Test Clock Input Timing Diagram . . . . . . . . . . . . . . . . 37

Figure 23. Boundary Scan (JTAG) Timing Diagram . . . . . . . . . . 38

Figure 24. Test Access Port Timing Diagram . . . . . . . . . . . . . . . 38

Figure 25. TRST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 26. Voltage Sequencing Case 1 . . . . . . . . . . . . . . . . . . . . 41

Figure 27. Voltage Sequencing Case 2 . . . . . . . . . . . . . . . . . . . . 42

Figure 28. Voltage Sequencing Case 3 . . . . . . . . . . . . . . . . . . . . 43

Figure 29. Voltage Sequencing Case 4 . . . . . . . . . . . . . . . . . . . . 44

Figure 30. Voltage Sequencing Case 5 . . . . . . . . . . . . . . . . . . . . 45

Figure 31. PLL Power Supply Filter Circuits . . . . . . . . . . . . . . . . 46

Figure 32. SSTL Termination Techniques . . . . . . . . . . . . . . . . . . 52

Figure 33. SSTL Power Value . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

MSC7118 数据表(PDF) 2 Page - Freescale Semiconductor, Inc

MSC7118 数据表(HTML) 2 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表下载