Electrical Characteristics

MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semiconductor

21

2.5.5

System Bus Access Timing

2.5.5.1

Core Data Transfers

Generally, all MSC8112 bus and system output signals are driven from the rising edge of the reference clock (REFCLK). The

is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of REFCLK (and T3 at the falling

edge), but the spacing of T2 and T4 depends on the PLL clock ratio selected, as Table 13 shows.

Figure 10 is a graphical representation of Table 13.

Figure 9. Timing Diagram for a Reset Configuration Write

Table 13. Tick Spacing for Memory Controller Signals

BCLK/SC140 clock

Tick Spacing (T1 Occurs at the Rising Edge of REFCLK)

T2

T3

T4

1:4, 1:6, 1:8, 1:10

1/4 REFCLK

1/2 REFCLK

3/4 REFCLK

1:3

1/6 REFCLK

1/2 REFCLK

4/6 REFCLK

1:5

2/10 REFCLK

1/2 REFCLK

7/10 REFCLK

Figure 10. Internal Tick Spacing for Memory Controller Signals

PORESET

Internal

HRESET

Input

Output (I/O)

SRESET

Output (I/O)

RSTCONF, CNFGS, DSISYNC, DSI64

CHIP_ID[0–3], BM[0–2], SWTE, MODCK[1–2]

Host programs

Word

SPLL is locked

(no external indication)

PORESET

Reset Configuration

pins are sampled

1

2

MODCK[3–5]

1 + 2

3

5

6

SPLL

locking period

Reset configuration write

sequence during this

period.

REFCLK

T1

T2

T3

T4

REFCLK

T1

T2

T3

T4

for 1:3

for 1:5

REFCLK

T1

T2

T3

T4

for 1:4, 1:6, 1:8, 1:10