PSD835G2-70UI datasheet(42/110 Pages) STMICROELECTRONICS

42 / 110 page

PSD835G2

PSD8XX Family

9.2.2.6 Input Micro

⇔Cells (IMCs)

The CPLD has 24 IMCs, one for each pin on Ports A, B, and C. The architecture of the IMC

is shown in Figure 14. The IMCs are individually configurable, and can be used as a latch,

outputs of the IMCs can be read by the microcontroller through the internal data bus.

The enable for the latch and clock for the register are driven by a multiplexer whose inputs

are a product term from the CPLD AND array or the MCU address strobe (ALE/AS). Each

product term output is used to latch or clock four IMCs. Port inputs 3-0 can be controlled by

one product term and 7-4 by another.

Configurations for the IMCs are specified by PSDsoft. Outputs of the IMCs can be read by

the MCU via the IMC buffer. See the I/O Port section on how to read the IMCs.

IMCs can use the address strobe to latch address bits higher than A15. Any latched

addresses are routed to the PLDs as inputs.

IMCs are particularly useful with handshaking communication applications where two

processors pass data back and forth through a common mailbox. Figure 15 shows a typical

configuration where the Master MCU writes to the Port A Data Out Register. This, in turn,

can be read by the Slave MCU via the activation of the “Slave-Read” output enable product

term. The Slave can also write to the Port A IMCs and the Master can then read the IMCs

directly. Note that the “Slave-Read” and “Slave-Wr” signals are product terms that are

derived from the Slave MCU inputs RD, WR, and Slave_CS.

The

PSD835G2

Functional

Blocks

(cont.)

OUTPUT

MICRO

⇔CELLS A

AND

MICRO

⇔CELL B

FEEDBACK

PORT

DRIVER

I/O PIN

INTERNAL DATA BUS

DIRECTION

MUX

ALE/AS

LATCH

INPUT MICRO

⇔CELL

ENABLE (.OE)

D FF

INPUT MICRO

⇔CELL _ RD

Figure 14. Input Micro⇔Cell

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