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HD74LS162AFPEL 数据表(PDF) 7 Page - Renesas Technology Corp |
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HD74LS162AFPEL 数据表(HTML) 7 Page - Renesas Technology Corp |
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7 / 11 page ![]() HD74LS162A Rev.3.00, Jul.15.2005, page 7 of 10 Waveforms 1 ƒ max, tPLH, tPHL, (Clock→Q, Ripple Carry) (Measure at tn + 10) (Measure at tn + 10) (Measure at tn + 1) (Measure at tn + 8) (Measure at tn + 4) (Measure at tn + 2) Ripple Carry Clock 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V 1.3V QA QB QC QD tTLH tPLH tPLH (Measure at tn + 9) tPLH (Measure at tn + 2) tPLH (Measure at tn + 4) tPLH (Measure at tn + 8) tPHL tPHL tPHL tPHL tPHL tw (CK) tTHL VOH VOL VOH VOL VOH VOL VOH VOL VOH VOL 0V 3V 10% 10% 90% 90% Note: Clock input pulse; tTLH ≤ 15 ns, t THL ≤ 6 ns, PRR = 1 MHz, duty cycle 50% and : ƒ max tTLH = tTHL ≤ 2.5 ns. tn is reference bit time when all outputs are low. |
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