HD74LS166A

Rev.4.00, May 10, 2006, page 2 of 7

Function Table

Inputs

Parallel

Internal outputs

Clear

Shift

Load

Clock

Inhibit

Clock

Serial

A

…H

Output

L

X

X

X

X

X

L

L

L

H

X

L

L

X

X

H

L

L

↑

X

a

…h

a

b

h

H

H

L

↑

H

X

H

H

H

L

↑

L

X

L

H

X

H

↑

X

X

Notes: 1. H; high level, L; low level, X; irrelevant

2.

↑; transition from low to high level

3.

a to h; the level of steady-state input at inputs A to H respectively

4.

established.

5.

↑ transition of the clock.