HD74LS166A

Rev.4.00, May 10, 2006, page 6 of 7

Waveform

Clock

Input

Clear

Input

Data

Input

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

1.3V

0V

3V

0V

3V

0V

3V

Notes:

1.

Input pulse;

≤ 15 ns, t

THL

≤ 6 ns, PRR = 1 MHz, duty cycle 50%

≥ 20 ns

≥ 20 ns, t

ƒ

2.

3.

Typical Clear, Shift, Load, Inhibit, and Shift Sequences

Serial Shift

Serial Shift

Clock Inhibit

Shift / Load

Load

Clock

Clear

Clear

Serial Input

Inhibit

B

A

H

HH

H

H

H

H

H

H

H

L

L

L

LLL

L

C

D

F

E

G

H

Parallel

Inputs