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HD74LS174 数据表(PDF) 2 Page - Renesas Technology Corp |
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HD74LS174 数据表(HTML) 2 Page - Renesas Technology Corp |
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2 / 9 page ![]() HD74LS174 / HD74LS175 Rev.3.00, Jul.15.2005, page 2 of 8 Pin Arrangement (Top view) VCC GND Clear 1Q 1D 2D 2Q 3D 3Q 6Q 6D 5Q 5D 4D 4Q Clock 15 16 1 2 3 4 5 6 7 14 8 9 10 11 12 13 (Top view) VCC GND Clear 1Q 1 Q 1D 2D 2 Q 2Q 4Q 4 Q 3D 4D 3 Q 3Q Clock 15 16 1 2 3 4 5 6 7 14 8 9 10 11 12 13 HD74LS174 CLR CK D Q CLR CK Q D CLR CK Q D CLR CK D Q Q D Q D CLR CK CLR CK HD74LS175 CLR QD D DD Q CLR Q Q CLR CK CK Q Q Q Q CLR CK CK Function Table Inputs Outputs Clear Clock D Q Q L X X L H H ↑ H H L H ↑ L L H H L X Q0 Q 0 Notes: 1. H; high level, L; low level, X; irrelevant 2. ↑; transition from low to high level 3. Q0; the level of Q before the indicated steady-state input conditions were established. 4. Q is applied to HD74LS175 only. |
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