HD74LS195AFPEL datasheet(6/8 Pages) RENESAS

部件名	HD74LS195AFPEL

功能描述	4-bit Parallel-Access Shift Register

PDF	8 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

标志

6 / 8 page

HD74LS195A

Rev.3.00, Jul.15.2005, page 6 of 7

Waveform

Clear

Clock

Data

Shift/Load

Outputs Q

1.3V

tTLH

tTHL

tPHL

tPLH

tPHL

tsu

trelease

tn+1

tTHL

tw (CLR)

VOH

VOL

10%

90%

90% 90%

tw (CK)

Notes:

Input pulse; tTLH

≤ 15 ns, t

THL

≤ 6 ns, PRR = 1 MHz, duty cycle 50%

A clear pulse is applied prior to each test.

Propagation delay times (tPLH and tPHL) are measured at tn + 1. Proper shifting of data is verified

at tn + 4 with a functional test.

J and

K inputs are tested the same as data A, B, C, and D inputs except that shift / load input

remains high.

tn; bit time beroer clocking transition.

tn + 1; bit time after one clocking transition.

tn + 4; bit time after four clocking transition.

HD74LS195AFPEL 数据表(PDF) 6 Page - Renesas Technology Corp

HD74LS195AFPEL 数据表(HTML) 6 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8

数据表下载