HD74LS259

Rev.2.00, Feb.18.2005, page 2 of 7

Pin Arrangement

(Top view)

GND

15

16

1

2

3

4

5

6

7

14

8

9

10

11

12

13

A

B

C

CLR

D

G

A

B

C

Data Input

Enable

Clear

Outputs

Outputs

Latch

Select

Function Table

Input

CLR

G

Output of

addressed latch

Each other output

Function

H

L

D

Qio

Addressable latch

H

H

Qio

Qio

Memory

L

L

D

L

8-line demultiplexer

L

H

L

L

Clear

Select inputs

C

B

A

Latch addressed

L

L

L

0

L

L

H

1

L

H

L

2

L

H

H

3

H

L

L

4

H

L

H

5

H

H

L

6

H

H

H

7

Notes: 1. H; high level, L; low level

2. D; the level at the data input

3.

… 7, as appropriate) before the indicated steady state input conditions were

established.