M38260E2FS datasheet(9/91 Pages) RENESAS

9 / 91 page

Rev.1.00

Sep 06, 2006

page 9 of 88

REJ03B0181-0100

3826 Group (One Time PROM version)

Table 4 Push and pop instructions of accumulator or processor status register

Accumulator

Processor status register

Push instruction to stack

PHA

PHP

Pop instruction from stack

PLA

PLP

Fig. 7 Register push and pop at interrupt generation and subroutine call

Note: Condition for acceptance of an interrupt request here

Execute JSR

On-going Routine

M (S)(PCH)

(S)

(S) – 1

M (S)(PCL)

Execute RTS

(PCL)M (S)

(S)

(S)– 1

(S)

(S) + 1

(S)

(S) + 1

(PCH)M (S)

Subroutine

POP return

address from stack

Push return address

on stack

M (S)(PS)

Execute RTI

(PS)M (S)

(S)

(S) – 1

(S)

(S) + 1

Interrupt

Service Routine

POP contents of

processor status

M (S)(PCH)

(S)

(S) – 1

M (S)(PCL)

(S)

(S) – 1

(PCL)M (S)

(S)

(S) + 1

(S)

(S) + 1

(PCH)M (S)

POP return

address

from stack

I Flag is set from “0” to “1”

Fetch the jump vector

Push return address

on stack

Push contents of processor

status register on stack

Interrupt request

(Note)

Interrupt enable bit corresponding to each interrupt source is “1”

Interrupt disable flag is “0”

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