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M66271FP 数据表(PDF) 2 Page - Renesas Technology Corp |
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M66271FP 数据表(HTML) 2 Page - Renesas Technology Corp |
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2 / 28 page  M66271FP REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page 2 of 27 Block Diagram 1 MPU I/F control circuit 2 6 3 4 5 12 11 14 9 7 78 79 Address buffer Data buffer (Basic timing control) Clock control Bus arbiter timing control (Cycle steal control) Control register LCD display timing control circuit LCD display data control circuit Oscillator output Oscillator input Wait MPU clock Bus high enable Reset 8/16 MPU select Read strobe Low write strobe High write strobe VRAM chip select Control register chip select MPU address bus A <13:0> D <15:0> MPU data bus IOCS MCS HWR LWR RD RESET BHE WAIT MPUSEL MPUCLK OSC1 OSC2 VRAM 9600-byte 69 70 71 72 66 67 68 62 61 LCDENB CP LP FLM M 1 80 65 64 51 41 10 13 24 25 35 40 32 76 75 74 33 36 37 38 39 73 8 23 34 42 52 53 77 VSS VDD N.C UD <3:0> LCD display data bus LCD control signal Display data transfer clock Display data latch pulse First line marker signal LCD alternating signal : : : : 43 60 31 15 22 26 50 53 Block Diagram 2 (In case of LCD module built-In system) 3 6 7 9 11 12 14 15 MPU I/F control circuit 2 4 5 78 79 20 22 _ 26 31 _ 53 60 _ Address buffer Data buffer (Basic timing control) Clock control Bus arbiter timing control Control register LCD display timing control circuit LCD display data control circuit Oscillator output Oscillator input Read strobe Low write strobe Control register chip select MPU address bus A <4:1> D <7:0> MPU data bus IOCS LWR RD OSC1 OSC2 VRAM 9600-byte 69 70 71 72 66 67 68 62 61 LCDENB CP LP FLM M 1 80 65 64 51 41 10 13 24 25 35 40 32 76 75 74 33 36 37 38 39 73 8 23 34 42 52 63 77 VSS VDD N.C UD <3:0> LCD display data bus LCD control signal Display data transfer clock Display data latch pulse First line marker signal LCD alternating signal No use pins VRAM address index register Data port register : : 16 19 43 50 |
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