M62333P/FP, M62338P/FP

REJ03D0865-0400 Rev.4.00 Mar 25, 2008

Page 4 of 9

I

Item

Symbol

Min

Max

Unit

SCL clock frequency

0

100

kHz

Time the bus must be free before a new transmission can start

4.7

—

µs

Hold time START condition

(After this period, the first clock pulse is generated)

4.0

—

µs

Low period of the clock

4.7

—

µs

High period of the clock

4.0

—

µs

Set-up time for START condition

(Only relevant for a repeated START condition)

4.7

—

µs

Hold time DATA

0

—

µs

Set-up time DATA

250

—

ns

Rise time of both SDA and SCL lines

—

1000

ns

Fall time of both SDA and SCL lines

—

300

ns

Set-up time for STOP condition

4.0

—

µs

Note:

Transmitter must internally provide at least a hold time to bridge the undefined region (300 ns Max) of the falling

edge of SCL.

Timing Chart

Start

Start

Start

Stop

SDA

SCL