M66313FP

REJ03F0179-0201 Rev.2.01 Mar 31, 2008

Page 3 of 9

Pin Arrangement

Parallel data

outputs

Serial data input

Output enable input

Latch enable input

Direct set input

Shift clock input

Serial data output

Parallel data

outputs

Parallel data

outputs

→ Q

7

→ Q

8

→ Q

9

→ Q

10

→ Q

11

→ Q

12

→ Q

13

→ Q

14

→ Q

15

→ Q

16

→ Q

17

→ Q

18

→ Q

19

→ Q

20

→ Q

21

→ Q

22

→ Q

23

→ Q

24

→ Q

25

→ Q

26

Q

7

Q

8

Q

9

Q

10

Q

11

Q

12

Q

13

Q

14

Q

15

Q

16

Q

17

Q

18

Q

19

Q

20

Q

21

Q

22

Q

23

Q

24

Q

25

Q

26

CK

→

S

Q

Q

Q

Q

Q

Q

Q

Q

Q

Q

Q

Q

OE →

LE →

A

→

CK

Q

1

SQ

32

S

D

Q

4

Q

3

Q

6

Q

5

Q

2

Q

27

Q

30

Q

29

Q

32

Q

31

Q

28

OE

LE

A

4

1

2

3

5

39

42

41

40

38

6

7

37

36

8

35

9

34

10

33

11

32

12

31

13

14

30

29

15

16

28

27

17

26

18

25

19

24

20

23

21

22

(Top view)

Outline: 42P2R-A

M66313FP

Parallel data

outputs

Functional Description

The employment of silicon gate CMOS process of the M66313FP guarantees low power dissipation and maintains high

noise margin as well as high output current and high speed required to drive LEDs.

Each shift register bit consists of a flip-flop for shifting and an output latch.

The shift operation takes place when the clock input CK changes from low-level to high-level.

The serial data input A corresponds to the data input of the first-stage shift register, and the shift register is shifted in

sequence when a pulse is applied to CK.

The parallel outputs

Q

If the latch-enable input

LE is turned high–level, the content of the shift register at that instant is latched.

If the direct set input

S

If the high-level input is applied to the output enable input

OE, Q

not set to the high-impedance state. The shift operation is not affected when

OE is changed.